This invention is related to my copending application Ser. No. 07/087,143, filed Aug. 19, 1987, now U.S. Pat. No. 4,885,719 for IMPROVED LOGIC CELL ARRAY USING CMOS E.sup.2 PROM CELLS.
This invention relates generally to application-specific integrated circuits (ASIC) and more particularly the invention relates to a logic cell array (LCA) ASIC.
ASIC devices are programmable integrated circuits which allow logic circuit designers speed and flexibility in designing logic arrays. Mask programmable gate arrays offer the highest degree of integration and flexibility, but have high, non-recurrent costs and require lengthy turn-around times. Field-programmable devices such as programmable array logic (PAL's) and programmable logic arrays (PLA's), and logic cell arrays (LCA's) provide faster turn-around at lower cost. However, the PAL and PLA implement only lower levels of integration with limited architectural flexibility.
The LCA is a reprogrammable device that implements complex digital logic functions and has logic capabilities equivalent to small arrays. The implementation of user logic inside the LCA is accomplished with writable memory (RAM) cells rather than dedicated integrated circuit masks (as with gate arrays) or programmable fuses (as with PAL's and PLA's). As described by Landry, "Logic Cell Arrays: High-Density, User-Programmable ASICs)," Technological Horizons, March 1986, the LCA produced by Xilinx Corporation consists of a matrix of configurable logic blocks which are arranged in rows and columns. Interleaved between rows and columns of the configurable logic blocks are user-definable interconnection resources (wiring paths) which provide the means for routing signals between the configurable logic blocks. Within each configurable logic block, a RAM is used to directly implement combinational logic functions, instead of the typical AND/OR gating function found in PAL's and PLA's. Arranged along the outside perimeter of the LCA die and surrounding the matrix of configurable logic blocks are input/output blocks. From an architectural point of view of LCA closely resembles a gate array in its organization yet retains the features and advantages of field-programmable logic devices.
Each cell of the conventional LCA consists of six transistors which necessitates a considerable chip area for each cell. Further, the cell provides static memory and requires reprogramming upon loss of power.
Disclosed in my copending application Ser. No. 07/087,143, supra is a logic cell and array using CMOS E.sup.2 PROM cells. The present invention is a similar cell and array which utilizes EPROM cells which are simpler in construction.